A semiconductor memory device has been continuously developed in order to increase the integration degree and the operation speed thereof. In order to increase the operation speed, a synchronous memory device has been introduced which can operate in synchronization with a clock supplied from the outside of a memory chip.
An early synchronous memory device is a single data rate (SDR) synchronous memory device which inputs/outputs data in synchronization with the rising edge of an external clock.
However, the SDR synchronous memory device could not sufficiently meet high-speed requirements of systems. In this regard, a double data rate (DDR) synchronous memory device has been introduced which processes two data in one clock cycle.
The DDR synchronous memory device successively inputs/outputs data in synchronization with the rising and falling edges of each clock cycle. Accordingly, without increasing the frequency of a clock, the DDR synchronous memory device can implement at least two times the bandwidth of the conventional SDR synchronous memory device. Hence, the DDR synchronous memory device can better accommodate high-speed operations.
The DDR synchronous memory device uses a multi-bit prefetch architecture for simultaneously processing multi-bit data. According to the multi-bit prefetch architecture, sequentially inputted data are aligned in parallel in synchronization with a data strobe signal, and the aligned multi-bit data are simultaneously stored in a memory cell array by a write command inputted in synchronization with an external clock signal.
In the multi-bit prefetch architecture, data needs to be aligned in synchronization with internal strobe signals DQS_R and DQS_F, and latched in synchronization with the final falling edge of a data strobe signal DQS.
As illustrated in FIG. 1, in the DDR synchronous memory device such as a DDR2 and a DDR3, the data strobe signal DQS is set to one of a logic low level LOW, a high-Z level Hi-Z and a logic high level HIGH before start of a preamble at time t1. When the data strobe signal DQS is set to the logic low level LOW before start of the preamble at time t1, a pulse of the internal strobe signal DQS_R is generated in synchronization with the rising edge of the data strobe signal DQS from the time t2 in point at which the preamble duration is completed.
When the data strobe signal DQS is set to the high-Z level Hi-Z Z or the logic high level HIGH before start of the preamble at time t1, a pulse may be generated in the internal strobe signal DQS_R during the preamble duration t1 to t2 as indicated by X1 and X2. This is because a circuit receiving the data strobe signal DQS to generate the internal strobe signal DQS_R is configured with a differential amplification circuit and differentially amplifies the data strobe signal DQS at the high-Z level Hi-Z or the logic high level HIGH.
If the internal strobe signal DQS_R is toggled in the preamble duration t1 to t2, an abnormal operation may occur when latching data in synchronization with the final falling edge of the data strobe signal DQS.